1. Field of the Invention
The present invention relates in general to a programmable read-only memory semiconductor device and the process for its fabrication. In particular, the present invention relates to a programmable read-only memory device having high memory cell density and its process of fabrication.
2. Technical Background
Read-only memory semiconductor devices, herein referred to as ROM devices, have been widely utilized in various types of digital equipment, ranging from mini-computer systems to microprocessor-based personal computer systems. ROM's are utilized to store programs or codes that are not to be altered under normal use conditions for these systems. The production of these ROM devices is normally designated by a customer, who supplies the code, or program, to be stored in the ROM device. In other words, the memory content of a particular ROM for a particular application is "programmed" at the factory which produces the ROM device.
The fabrication of a ROM IC is a relatively complicated process. Many of the fabrication steps take considerable time and involve special processing of the utilized material as well as requiring strict control of the processing environment. When manufacturing ROM IC devices of the same model, fabrication procedural steps are generally the same, the only differences between specific devices being in the memory contents to be programmed. The programing of the ROM memory content in the fabrication process of a ROM IC device is at the final stage of the entire process. Therefore, it is possible to manufacture a large quantity of a particular ROM IC device up to the stage of programming storage content, and then temporarily store such fabricated devices until the designation of the memory content. In this way, the production of code-containing ROM IC's may appear to a customer to be a fast process. A manufacturer has only to prepare the corresponding photomasks for the particular program content and execute the programming procedure.
Generally, the actual process of programming a ROM IC device to contain a designated code content involves implanting impurities of selected conductance type into selected memory cell transistors of the ROM IC. The selection of the memory cell transistor to be subjected to the ion implantation procedure corresponds to the code content when the ROM IC device is read accessed. The implanting of the impurities in the memory cells determines the read result of either an ON-state or an OFF-state of the memory cell transistor. The state of impurity implantation decides the ON-state or the OFF-state. The concentration of the impurity implantation is, however, a difficult process to control. An improper level of impurity concentration will affect the code contents in the form of binary 1's and 0's, and, in turn, the reliability of the ROM IC device. The process of "memory content implantation" involves the preparation of a photomask, which is a translated version of the code content that the ROM IC device is required to hold. In addition, all the programing procedures must be concluded before the ROM IC device can be packaged into its protective carrier.
Another alternative transistor-based ROM IC memory device programming methodology involves employing a switch layer integral to the ROM IC device such that micro-switches are formed using dielectric material. A dielectric micro-switch layer is fabricated to be in contact with the metal contact of each of the memory cells in the ROM IC device memory array, so as to control the ON and OFF status of the memory cell transistors. By selectively controlling the ON and OFF status of the micro-switches in the switch layer, the designated memory cells may be "programmed" to be in either the required ON or OFF status. For a more in-depth description of this programing concept, to which the present invention is related, refer to FIG. 1 of the accompanying drawing of the present invention.
FIG. 1 schematically shows in cross-sectional view a ROM semiconductor device fabricated in accordance with the prior art switch layer technique. The memory cell for the prior art ROM IC device includes semiconductor substrate 1, which in this depicted example is a P-type substrate, having the memory cell transistors fabricated thereon. Specifically, N-type drain 10, N-type source 12, as well as channel region 14 for the memory cell between source 12 and drain 10 are fabricated on P-type substrate 1.
The cell unit includes gate structure 102, having gate oxide layer 16 and gate electrode 18. Gate electrode 18 constitutes a word line in this memory cell. The cell unit also includes a layer of phosphosilicate glass 104 (PSG) which covers gate structure 102 and field oxide 100 and serves as an insulator. The cell unit further includes switch control layer 19, a dielectric material fabricated on top of N-type drain 10. Metal material is then formed over the surface of switch control layer 19 to constitute bit line 11, and is also formed over the surface of N-type source 12 to constitute ground line 13.
Referring to FIGS. 2a and 2b, equivalent circuits of the prior art ROM device memory cell in its OFF and programmed ON status, respectively, are shown. In FIG. 2a, the equivalent circuit of the memory cell indicates that the transistor comprising the core for the cell is tied to the memory array of the ROM device via both bit line 11 and word line 18.
The connection of the memory cell transistor to device bit line 11 is through an equivalent switch involving the dielectric switch control layer, and is expressed as the capacitor in the equivalent circuit of FIG. 2a. Dielectric switch control layer 19, when its region corresponding to the memory cell is maintained intact in its dielectric layer form, acts as a blocking capacitor between the source/drain of the transistor and bit line 11. When the dielectric layer at the region of the memory cell is punched through by an excessive electric potential applied thereon, the equivalent capacitor becomes a conducting switch that electrically connects the source/drain of the cell transistor to the bit line, thereby representing an ON transistor in the cell unit.
Thus, when a ROM IC device is not yet programmed to contain the code it is required to hold, each of its memory cells has its equivalent dielectric switch maintained at an equivalent OFF state, thereby turning off the cell transistor. FIG. 2a of the equivalent circuits represent this OFF status of the memory cell. When, however, a memory cell is required to be programmed, its equivalent capacitor is then punched through to become a conducting switch by the application of a programming voltage, and the memory cell becomes an equivalent circuit of FIG. 2b.
To fabricate switch control layer 19 and allow it to be made integral to the entire ROM IC device, a particular layer of photomasking must be prepared for the process. This photomasking preparation adds to the complexity of the fabrication procedure, as well as to the cost. Also, since the core of the memory cell of the ROM device is a transistor which requires a certain amount of die space, the usage of such transistors to form memory cell ON/OFF states constitutes an obstacle to device miniaturization.